HIGH-PERFORMANCE COMPILER-DRIVEN CONCURRENT FAULT SIMULATION WITH ACTIVITY-DIRECTED PARALLEL PATTERN EVALUATION

W. Hahn, A. Hagerer, R. Kandlbinder
Faculty of Mathematics and Computer Science, University of Passau
Innstr. 33, 94032 Passau, F.R. Germany
E-mail: hahn@perm.fmi.uni-passau.de

ABSTRACT

The Munich Simulation Computer, a highly-parallel system, has been an approach to speed up logic simulation. Most recent work has been devoted to hardware-accelerated concurrent fault simulation. This paper shows that the strategy of compiler-driven simulation can be combined with the concept of event-(activity)-directed simulation (selective trace simulation) not only for logic simulation but also for concurrent fault simulation. Furthermore, by the parallel-pattern/multiple-fault-propagation algorithm, a MuSiC version with 256 processing units can offer a simulation performance of 10E+8 test-vectors times gates evaluated per second.