Field Programmable Devices: Design and Simulation
Tutorial at ESS 99 by
Dietmar P.F. Möller and Christian Siemers,
University of Hamburg, Dept. Computer Science
Chair: Computer Engineering
Vogt-Kölln-Str. 30, D-22527 Hamburg
email: dietmar.moeller@informatik.uni-hamburg.de
siemers@fh-westkueste.de
Two complex topics in one tutorial – this is the translation of the headline. But the reasons to present this in that specific way are very convincing: VHDL is a modeling and simulation language with some extends to synthesize the model into hardware, and Field Programmable Logic Devices are programmable hardware which could be programmed to their final state using VHDL.
The combination of both presents on one hand a new kind of programmability in the design and simulation domain. The developer community is used to associate the word ‘programmability’ with a computer system containing sequential working processors. The processors with their increasing performance and clock rates are able to satisfy most requests but not all. Therefore we´ll show another way: Hardware is no longer hardwired but programmable, and hardware has built-in parallelism. It is possible to compute problems direct in hardware with a speed-up of more than 1000, compared with processors. This seminar presents Field Programmable Logic Devices (FPLD) as well as the Very High Speed Integrated Circuits Hardware Description Language (VHDL).
There is another view due to the combination. As VHDL is a simulation language with a sophisticated simulation concept, it could be used to model and simulate not only electronical systems. Normally the simulation runs on sequential working computer systems reaching simulation times in the area of months, and this opens the idea of co-simulation: Part of the code is synthesized to an FPLD and will executed with an improved performance, while the other, for example the graphical interface, remains in software. This opens a new area of simulation based hard-ware/software co-design strategies and applications.
Nevertheless it is not an easy task to introduce both simultaneously. This time-limited tutorial offers nothing more nothing less than first impressions and ideas, and for everyone interested in these topics it should be only the starting point. Hence the participants will recieve a CD-ROM with an
as well as a run time version of a simulation tool for first own FPLD/VHDL design studies.
Tutorial at ESS 99 by
Dietmar P.F. Möller and Matthias Reuter,
University of Hamburg, Dept. Computer Science
Chair: Computer Engineering
Vogt-Kölln-Str. 30, D-22527 Hamburg
email: dietmar.oeller@informatik.uni-hamburg.de
email: reuter@informatik.uni-hamburg.de
The application of hyperclassification based on neural networks in supervision and control of technical processes requires not only the ability to classify states of process and to identify possible faulty or dangerous states but also the possibility to monitor the changes of the process variables over time in order to predict the very earling development of dangerous states. One way to store real time behaviour in a neural net hyperclassification structure is based on the learning strategy of sensitization as part of preprocessing.
Using DLS or FD-spectra is a very simple way to calculate feature specific repre-sentations which can be used as preprocessing step for neural nets to minimize the necessary learning steps by a factor up to 100. But it is most important for the resolution of theses representations and the study of the real time behaviour to chosse the right parameters for calculating the DLS, FD- and TTY-spectra.
The combination of hyperclassificaton, neural nets, sensitization and preprocessing algorithms presents on one hand a new kind of methodology in the design and smulation domain of process control.
Nevertheless it is not an easy task to introduce this fourth simultaneously. This time-limited tutorial offers nothing more nothing less than first impressions and ideas, and for everyone interested in these topics it should be only the starting point. Hence the participants will recieve a documentation dealing
as well as a run time version of a simulation tool for design studies.