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Automated generation of decision trees for decoding irregular instruction sets

• Lillian Tadros

(2024). ECMS 2024, 38th Proceedings
Edited by: Daniel Grzonka, Natalia Rylko, Grazyna Suchacka, Vladimir Mityushev, European Council for Modelling and Simulation.
DOI: http://doi.org/10.7148/2024
ISSN: 2522-2422 (ONLINE)
ISSN: 2522-2414 (PRINT)
ISSN: 2522-2430 (CD-ROM)
ISBN: 978-3-937436-84-5
ISBN: 978-3-937436-83-8 (CD) Communications of the ECMS Volume 38, Issue 1, June 2024, Cracow, Poland June 4th – June 7th, 2024

https://doi.org/10.7148/2024-0459

Lillian tadros (2024). Automated Generation of Decision Trees for Decoding Irregular Instruction Sets, ECMS 2024, Proceedings Edited by: Daniel Grzonka, Natalia Rylko, Grazyna Suchacka, Vladimir Mityushev, European Council for Modelling and Simulation. doi:10.7148/2024-0459

Instruction decoders are an integral part of the SoC design flow as elements of processor toolchains and instruction set simulators. The strenuous and error-prone process of manual decoder design can be greatly mitigated by automated decoder generation tools based on high level instruction definitions. Unfortunately, automatic generation is challenged by the growing complexity of instruction sets as well as irregularities such as non-uniform opcodes, logic propositions on bit fields and multiple or nested specializations. The few available state-of-the-art decoder generation tools either cannot be applied to irregular instruction sets, or produce partially wrong results. As to performance, they either attempt no optimization, make heavy use of heuristics or adopt unsatisfactory cost models. This paper presents two algorithms for generating decoders for irregular instruction sets that produce functionally correct decoders with acceptable cost. Our algorithm has been successfully applied to the SPARC, MIPS32 and ARMv7 instruction sets.